The present invention relates to an improved input circuit protected against an input signal having a high voltage exceeding a breakdown voltage thereof, and more particularly relates to specific measures taken not to delay the propagation of signals transmitted therethrough even if the power supply voltage thereof is reduced.
In recent years, as the size of semiconductor large-scale integrated circuits (hereinafter, abbreviated as an "LSI's"), which an input circuit is made up of, has been drastically reduced, individual MOS transistors, which are integrated in each single LSI, have also been downsized correspondingly. In an MOS transistor of such an extremely small size, the breakdown voltage of the gate oxide film thereof is much lower than what it used to be, and is almost inoperative with a conventional power supply voltage. Accordingly, as such everlasting downsizing of LSI's proceeds, a power supply voltage for operating an input circuit goes on decreasing from 5 V, which was a commonplace until just recently, into 3.3 V and then into 2.5 V. Under the latest circumstances such as these, it is not unusual that brand-new miniaturized LSI's, operating at a reduced voltage like 3.3 V, and conventional LSI's, operating at 5 V as ever, coexist within a single semiconductor device. Thus, the output of an LSI operating at 5 V might possibly be supplied to an LSI operating at 3.3 V. If the gate oxide film of an LSI operating at 3.3 V is poorly resistant to a voltage as high as 5 V, then the film is very likely to deteriorate and eventually causes dielectric breakdown. In view of this state in the art, input circuits of various types have been designed to eliminate problems caused by the input of a signal with a voltage exceeding a nominal breakdown voltage.
Hereinafter, a prior art input circuit will be described with reference to the drawings. FIG. 4 is an electric circuit diagram illustrating a configuration for a prior art input circuit.
As shown in FIG. 4, an input signal IN is received at an input terminal Tin of an input circuit 100 from the outside of an LSI. And an output signal OUT is transmitted to other internal circuits within the LSI through an output terminal Tout of the input circuit 100. A power supply voltage Vdd is supplied through a power supply terminal 103 into the input circuit 100. The input circuit 100 further includes: an n-channel MOS transistor (NMOSFET) 101; a p-channel MOS transistor (PMOSFET) 106; and a controller 105, implemented as an inverter 107, for controlling the gate voltage at the PMOSFET 106. In the illustrated example, the power supply voltage Vdd supplied through the power supply terminal 103 is supposed to be. 3.3 V and the gate oxide film of each MOS transistor included in the input circuit 100 is supposed to have a breakdown voltage of 3.6 V. In general, the breakdown voltage of a gate oxide film is usually defined to have some margin with respect to a power supply voltage. Accordingly, as is also the case with this circuit 100, the breakdown voltage of the gate oxide film of each MOSFET included in an LSI operating with a power supply voltage of 3.3 V is often defined at about 3.6 V.
Next, the operation of the input circuit 100 having such a configuration will be described with reference to FIG. 4.
If an input signal IN with a voltage of 5 V is received at the input terminal Tin, a voltage at one terminal of the NMOSFET 101, closer to the inverter 107, increases. However, at a point in time the input voltage of the inverter 107 reaches a voltage (Vdd-Vtn) obtained by subtracting the threshold voltage. Vtn of the NMOSFET 101 from the power supply voltage Vdd, the NMOSFET 101 turns OFF. In this case, a back bias effect is caused. Accordingly, supposing the threshold voltage Vtn of the NMOSFET 101 is 1 V, the NMOSFET 101 turns OFF when the input voltage of the inverter 107 reaches 2.3 V. On the other hand, supposing the switching voltage Vsw of the inverter 107 is equal to one half of the power supply voltage Vdd (i.e., (Vdd/2)), the switching voltage Vsw is 1.65 V. In this case, since the input voltage of the inverter 107 is 2.3 V, the inverter 107 inverts an H-level signal to output an L-level signal. In response thereto, the PMOSFET 106 turns ON and the input voltage of the inverter 107 further increases up to 3.3 V. In such a state, a gate voltage Vg1 at the NMOSFET 101 is 3.3 V. Accordingly, the substrate potential and the gate potential, sandwiching the gate oxide film therebetween, are 5 and 3.3 V, respectively, i.e., the potential difference across the gate oxide film of the NMOSFET 101 is 1.7 V. Thus, the potential difference across the gate oxide film does not exceed its breakdown voltage of 3.6 V. In any other transistor in the input circuit 101, the potential difference across the gate oxide film thereof does not exceed the breakdown voltage thereof. As a result, the L-level signal is output through the output terminal Tout.
Alternatively, if an input signal IN with a voltage of 0 V is received at the input terminal Tin, the input voltage of the inverter 107 is also 0 V. Thus, the inverter 107 outputs an H-level signal with a voltage of 3.3 V to turn the PMOSFET 106 OFF. Even in such a state, the potential difference across the gate oxide film does not exceed the breakdown voltage thereof in any transistor in the input circuit 101, either. As a result, the H-level signal is output through the output terminal Tout.
As can be understood, even if a voltage, exceeding the breakdown voltage of the gate oxide film of an MOS transistor included in an LSI, is supplied, above problems do not happen in this conventional input circuit.
This input circuit, however, is non-operative if the power supply voltage Vdd is reduced. FIG. 5(a) is graph illustrating respective variations in gate voltage Vg1 of the NMOSFET 101 and switching voltage Vsw and input voltage Vii of the inverter 107 with a power supply voltage Vdd in the conventional input circuit 100. In FIG. 5(a), the axis of abscissas indicates the power supply voltage Vdd and the axis of ordinates indicates voltages at respective parts. The switching voltage Vsw of the inverter 107 is in proportion to the power supply voltage Vdd. For example, when the power supply voltage Vdd is 3.3 V, the switching voltage Vsw is 1.65 V. The input voltage Vii of the inverter 107 is obtained by subtracting the threshold voltage Vtn of the NMOSFET 101 from the power supply voltage Vdd. For instance, when the power supply voltage Vdd is 3.3 V, the input voltage Vii is 2.3 V. At the power supply voltage of 3.3 V, since the input voltage Vii (2.3 V) of the inverter 107 is higher than its switching voltage Vsw (1.65 V), the inverter 107 inverts the signal level from high into low to turn the PMOSFET 106 ON. However, if the power supply voltage Vdd is around 2 V, then the input voltage Vii of the inverter 107 may be lower than the switching voltage Vsw, considering the variation in power supply voltage Vdd. In FIG. 5(a), the range where Vii is lower than Vsw is identified by Roff. Accordingly, the inverter 107 sometimes might be non-operative.
FIG. 5(b) is a graph illustrating a relationship between the power supply voltage Vdd and the propagation delay time tde of the input signal IN in the conventional input circuit 100. In FIG. 5(b), the axis of abscissas indicates the power supply voltage Vdd and the axis of ordinates indicates the propagation delay time tde. As shown in FIG. 5(b), if the switching voltage Vsw of the inverter 107 is Vdd/2, as the power supply voltage Vdd is lowered, the delay time tde drastically increases. In particular, when the power supply voltage Vdd reaches around 2 V, the delay time tde starts to increase even more abruptly, since the input voltage Vii of the inverter 107 is closer to the switching voltage Vsw. It should be noted that if the switching voltage Vsw of the inverter 107 is lowered to Vdd/3, then such an abrupt increase in delay time can be suppressed as represented by the broken lines in FIGS. 5(a) and 5(b).
However, in order to get the level inversion of the input signal done by the inverter 107 from high into low, or vice versa, the switching voltage Vsw of the inverter 107 cannot be lower than a certain limit. Accordingly, it is difficult for the conventional input circuit to radically solve the problems caused by the use of a power supply voltage Vdd making the input voltage Vii of the inverter 107 lower than the switching voltage Vsw thereof.